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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) 256 mb synchronous dram description
is42s83200a is a synchronous 256mb sdram and is organized as 4-bank x 8,388,608-word x 8-bit; and is42s16160a is organized as 4-bank x 4,194,304-word x
16-bit. all inputs and outputs are referenced
to the rising edge of clk.
features is42s83200a and is42s16160a achieve very high speed clock rates up to 166mhz, and are suitable for main memories or graphic memories in computer systems. - single 3.3v 0.3v power supply - max. clock frequency: -6:166mhz<3-3-3> - fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by ba0,ba1(bank address) - /cas latency- 2/3 (programmable) - burst length- 1/2/4/8/fp (programmable) - burst type- sequential and interleave burst (programmable) - byte control- dqml and dqmu (is42s16160a) - random column access - auto precharge / all bank precharge controlled by a10 - auto and self refresh - 8192 refresh cycles /64ms(4 banks concurrent refresh) - lvttl interface - row address a0-12 /column address a0-9(x8) / a0-8(x16) - package: 400-mil, 54-pin thin small outline (tsop ii) with 0.8mm lead pitch item -6 -7 -75 unit tclk clock cycle time (min.) cl=2 - - 10 ns cl=3 6 7 7.5 ns tras active to precharge command period (min.) 42 45 45 ns trcd row to column delay (min.) 15 20 20 ns tac access time from clk (max.) cl=2 - - ns cl=3 5 5.4 5.4 ns trc ref /active command period (min.) 60 63 67.5 ns icc1 operation current (single bank) (max.) is42s83200a 110 ma is42s16160a 130 130 ma icc6 self refresh current (max.) -6,-7,-75 3 3 ma 6 3 is42s83200a/16160a - - - - lead-free available -7:143mhz<3-3-3> -75:133mhz<3-3-3>
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) pin configura tion (t op view)? c lk : m ast er c l o c k
c k e : c lo ck e n able
/ cs : ch i p s e l e c t
/ ras : ro w ad d r e s s s t r o b e
d q m, d q mu /l : o utp ut d i sabl e / w r i te m ask a0 - 1 2 : ad d r e s s i n p u t ba0 , 1 : ba n k ad d r e s s i n p u t vd d : po w e r s u p p l y / c a s : c ol u m n a dd re s s s t robe v d dq : p ow e r s up pl y f or o u t pu t
/ w e : w r ite e n ab le v s s : g r o und
d q 0- 15 : d a t a i/o vs s q : g r o u n d f o r o u t p u t
x8 x16 vdd vdd vss vss dq0 dq0 dq15 dq7 vddq vddq vssq vssq nc dq1 dq14 nc dq1 dq2 dq13 dq6 vssq vssq vddq vddq nc dq3 dq12 nc dq2 dq4 dq11 dq5 vddq vddq vssq vssq nc dq5 dq10 nc dq3 dq6 dq9 dq4 vssq vssq vddq vddq nc dq7 dq8 nc vdd vdd vss vss nc dqml nc nc /we /we dqmu dqm /cas /cas clk clk /ras /ras cke cke /cs /cs a12 a12 ba0 ba0 a11 a11 ba1 ba1 a9 a9 a10/ap a10/ap a8 a8 a0 a0 a7 a7 a1 a1 a6 a6 a2 a2 a5 a5 a3 a3 a4 a4 vdd vdd vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 40 0mi lx8 75m il 54 pin 0. 8mm pit ch ts op(i i)
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) block diagram dq0-7 address buffer control signal buffer clock buffer control circuitry i/o buffer mode register memory array bank #0 8192x1024x8 cell array memory array bank #1 cell array memory array bank #2 cell array memory array bank #3 cell array 8192x1024x8 8192x1024x8 8192x1024x8 a0-12 ba0,1 clk cke / c s /ras /cas /we dqm note:this figure shows the is42s83200a the is42s16160a configuration is 8192x512x16 of cell array and dq0-15
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) pin function
clk input master clock: all other inputs are referenced to the rising edge of clk cke input clock enable: cke controls internal clock.when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self-refresh. after self-refresh mode is started, cke becomes asynchronous input. self-refresh is maintained as long as cke is low. / c s input chip select: when /cs is high, any command means no operation. / r a s , / c a s , / w e input combination of /ras, /cas, /we defines basic commands. a0-12 input a0-12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-12. the column address is specified by a0-9(x8)/a0-8(x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. b a 0 , 1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre , read , write commands. dq0-7(x8), dq0-15(x16) input / output data in and data out are referenced to the rising edge of clk. dqm(x8), dqmu/l(x16) input din mask / output disable: when dqm(u/l) is high in burst write, din for the current cycle is masked. when dqm(u/l) is high in burst read, dout is disabled at the next but one cycle. vdd, vs s power supply power supply for the memory array and peripheral circuitry. vddq, vs s q power supply vddq and vssq are supplied to the output buffers only.
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) basic functions? the is42s83200a/16160a provides basic ? functions, bank (row) activate, burst read / write, bank (row) ? precharge, and auto / self refresh.? each command is defined by control signals of /ras,? clk /cas and /we at clk rising edge. in addition to 3 signals,? /cs, cke and a10 are used as chip select, refresh opt ion,? and precharge option, respectively .? to know the detailed definition of commands,? please see the command truth table.? /cs chip select : l=select, h=deselect /ras command /cas command define basic command /we command cke refresh option @ refresh command a10 precharge option @ precharge or read/write command activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto-precharge, reada ). write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this com- mand also terminates burst read / write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically.
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) command truth t able? command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11-12 note deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all banks prea h x l l h l x h x column address entry & write write h x l h l l v l v column address entry & write with auto-precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto-precharge reada h x l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate tbst h x l h h l x x x mode register set mrs h x l l l l l l v 1 h=high level, l=low level, v=valid, x=don't care, n=clk cycle number note: 1. a7-9,11-12=l, a0-a6 =mode address
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) function truth t able? current state /cs /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l x tbst nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state /cs /ras /cas /we address command action write h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state /cs /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea nop*4 (idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state /cs /ras /cas /we address command action re - freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock ccle and the current clock ccle. 2. illegal to bank in specified state; function ma be legal in the bank indicated b ba, depending on the state of that bank. 3. must satisf bus contention, bus turn around, write recover requirements. 4. nop to bank precharging or in idle state. ma precharge bank indicated b ba. 5. illegal if an bank is not idle. illegal = device operation and/or data-integrit are not guaranteed.
integrated silicon solution, inc. ? 1-800-379-4774 11 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) function truth t able (continued) current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain power down) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle*3 l h x x x x x exit clk suspend at next cycle*3 l l x x x x x maintain clk suspend abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously . a minimum setup time must b e satisfied before any command other than exit. 2. self-refresh can be entered only from the all banks idle state. 3. must be legal command.
12 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) simplified st a te diagram
refs self refresh ckel ckeh ckel ckeh ckel ckeh ckel ckeh act refa refsx ckel ckeh mrs ckel ckeh write read writea writea reada write read pre reada writea reada pre pre pre power applied automatic sequence command sequence clk suspend mode register set idle auto refresh write suspend write writea suspend writea power on pre charge reada read read suspend row active power down reada suspend term term
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm high and nop condition at the inputs. 2. maintain stable power, stable clock, and nop input conditions for a minimum of 200s. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when all banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. clk /cs /ras /cas /we ba0,1 a12-a0 v ba0 ba1 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 sw 0 0 ltmode bt bl burst length bl bt=0 bt=1 0 0 0 0 0 1 0 1 0 0 1 1 10 0 10 1 11 0 11 1 1 2 4 8 r r r full page 1 2 4 8 r r r r 0 1 burst type sequential interleaved latency mode cl /cas latency 0 0 0 0 0 1 0 1 0 0 1 1 10 0 10 1 11 0 11 1 r r 2 3 r r r r burst write single write sw 0 1 r: reserved for future use
14 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) clk command address dq read y write y /cas latency burst length burst length cl= 3 bl= 4 q0 q1 q2 q3 d0 d1 d2 d3 burst type a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 - 0 - 1 - 0 - 1 - 0 0 2 5 1 4 1 3 6 0 5 2 4 7 3 6 3 5 0 2 7 4 6 1 5 0 5 7 2 4 1 6 0 3 7 2 7 1 0 2 1 3 2 0 3 0 7 6 0 1 1 0 2 3 3 0 - 1 1 1 3 4 3 1 1 8 4 2 0 0 1 1 0 0 1 1 0 0 1 1 - 1 4 3 0 7 6 3 2 7 6 5 2 5 4 1 0 7 2 3 6 7 4 3 6 5 2 1 0 1 0 5 4 7 4 7 6 3 2 1 0 1 4 5 6 5 0 7 4 3 2 7 6 3 2 1 6 1 0 5 4 3 6 7 2 3 0 7 2 1 6 5 4 5 4 1 0 3 0 2 1 3 2 0 3 1 0 1 4 5 3 2 2 3 1 0 2 1 - 2 0 6 5 0 1 2 0 0
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) operational description bank activate the sdram has four independent banks. each bank is activated by the act command with the bank ad- dresses (ba0,1). a row is indicated by the row ad- dresses a0-12. the minimum activation interval be- tween one bank and the other bank is trrd.multiple banks can be active state concurrently by issuing mul- tiple act commands. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea, pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued.ba0-1 are dont care in this case. read after trcd from the bank activation, a read command can be issued. 1st output data is avail- able after the /cas latency from the read, fol lowed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a0-9(x8), a0-8(x16) , and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl after reada. the next act command can be issued after (bl + trp) from the previous reada.
in any case, trcd+bl
ba n k a ct i vat i o n an d pr ech ar g e a l l (bl = 4, c l = 3 ) clk command a0-9,11-12 a10 ba0-1 dq act read act pre act xa xb yb xa 1 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trrd trcd trp xa precharge all
16 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) act read act pre act xa xb yb xa 0 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trcd trcd trp xa mu l ti ban k i n te rl eav i n g r ead (cl = 2, b l = 4 ) read ya 0 00 qa0 qa1 qa2 qa3 00 clk command a0-9,11-12 a10 ba0-1 dq re ad w i th au to -prec h a rg e (cl = 2, b l = 4 ) clk command a0-9,11-12 a10 ba0-1 dq internal precharge starts a u to -pr e c h a r g e t i m i n g (r ea d , b l =4 ) clk command dq act act xa xa xa 00 00 trcd trp xa read ya 1 00 qa0 qa1 qa2 qa3 bl act act trcd read qa0 qa1 qa2 qa3 bl qa0 qa1 qa2 qa3 cl=2 cl=3 dq internal precharge starts
integrated silicon solution, inc. ? 1-800-379-4774 17 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) write a write command can be issued to any active bank. the start address is specified by a0-9(x8), a0-8(x16). 1st input data is set at the same cycle as the write. the consecutive data length to be write is defined by the burst length. the address sequence of burst data is defined by burst type. minmum delay time of a write command after an act command to the same bank is trcd. from the last input data to the pre command , the write recovery time (twr) is required. when a10 is high at a write command , auto-precharge (writea) is performed. any com- mand (read,write,pre,act,tbst) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at twr after the last input data cycle . the next act command can be issued after (bl+twr-1+trp) from the previous writea. in any case, trcd+bl+twr-1 trasmin must be met. wr it e (b l= 4 ) clk command a0-9,11-12 a10 ba0-1 dq wr it e w it h a u to- pr e c ha r ge (b l= 4 ) clk command a0-9,11-12 a10 ba0-1 dq act pre act xa xa 0 xa 00 00 trcd trp xa write ya 0 00 da0 da1 da2 da3 bl twr act act xa xa xa 00 00 trcd trp xa write ya 1 00 da0 da1 da2 da3 bl twr internal precharge starts
18 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any bank. random column access is allowed read to read interval is minimum 1 clk.. re ad i n terr u p ted b y rea d (cl = 2, bl = 4) clk command a0-9,11-12 a10 ba0-1 dq read yb 0 00 qc0 qc1 qc2 qc3 read ya 0 00 qa0 qa1 qa2 qb0 read yc 0 10 [ read interrupted by w rite ] burst read operation can be interrupted by write of any bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 2 cycle after write assertion. r e a d int e r r u pt e d b y wr it e (c l= 2 , b l= 4 ) clk command a 0-9,11-12 a10 ba0-1 dqm dq act xa xa 00 read ya 0 00 qa0 da0 da1 da2 write ya 0 00 da3 output disable by dqm by write
integrated silicon solution, inc. ? 1-800-379-4774 19 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same bank . read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=4. re ad i n terr u p ted b y pr ech ar g e (b l = 4 ) clk command pre read q0 q1 q2 pre read q0 q1 pre read q0 pre read q0 q1 q2 pre read q0 q1 pre read q0 c l=2 c l=3 dq command dq command dq command dq command dq command dq
20 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) [read interrupted by burst terminate] similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. the terminated bank remains active. read to tbst interval is minimum 1 clk. a tbst command to output disable latency is equivalent to the /cas latency. re ad i n terr u p ted b y t er mi n a te (bl = 4) c l=2 c l=3 clk command dq command dq command dq command dq command dq command dq tbst read q0 q1 q2 tbst read q0 q1 tbst read q0 tbst read q0 q1 q2 tbst read q0 q1 tbst read q0
integrated silicon solution, inc. ? 1-800-379-4774 21 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) [ w rite interrupted by w rite ] burst write operation can be interrupted by new write of any bank. random column access is allowed. write to write interval is minimum 1 clk. wr it e i nt e r r up te d by w r i te (b l = 4 ) clk command a 0-9,11-12 a10 ba0-1 dq write yb 0 00 dc0 dc1 dc2 dc3 write ya 0 00 da0 da1 da2 db0 write yc 0 10 [ w rite interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". wr it e i nt e r r up te d by r e a d (c l= 2 , b l= 4 ) clk command a0-9,11-12 a10 ba0-1 dq act xa xa 00 read yb 0 00 da0 da1 qb0 write ya 0 00 qb1 qb2 qb3 don't care
22 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank.write recovery time(twr) is required from the last data to pre command. during write recovery, data inputs must be masked by dqm. w ri te i n ter ru p te d b y prec h a rg e (bl = 4) clk command a0-9,11-12 a10 ba0-1 dqm dq write ya 0 00 act xa 0 00 da0 da1 pre 0 00 act xa 0 00 twr trp [write interrupted by burst terminate] burst terminate command can terminate burst write operation.in this case, the write recovery time is not required and the bank remains active. write to tbst interval is minimum 1 clk. wr it e i nt e r r up te d by t e r m ina te (b l= 4 ) clk command a0-9,11-12 a10 ba0-1 dq write ya 0 00 act xa 0 00 da0 da1 tbst write yb 0 00 db0 db1 db2 db3
integrated silicon solution, inc. ? 1-800-379-4774 23 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) [write with auto-precharge interrupted by write or read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after(bl+twr-1+ trp) from the writea. auto-precharge interruption by a command to the same bank is inhibited. wr it ea int e r r u pt e d b y wr ite t o a not h e r b a n k (b l = 4 ) clk command a0-9,11-12 a10 ba0-1 dq db0 db1 db2 db3 write ya 1 00 da0 da1 write yb 0 10 bl twr trp act xa xa 00 auto-precharge interrupted activate wr it ea int e r r u pt e d b y r ea d to a n ot he r ba nk (c l= 2 , b l= 4 ) clk command a 0-9,11-12 a10 ba0-1 dq write ya 1 00 da0 da1 read yb 0 10 bl twr trp act xa xa 00 qb0 qb1 qb2 qb3 auto-precharge interrupted activate
24 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) [read with auto-precharge interrupted by read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after (bl+trp) from the reada. auto-precharge interruption by a command to the same bank is inhibited. re a da i n te rru p ted b y re a d to an o th er b an k ( cl = 2, bl = 4) clk command read ya 1 00 qa0 qa1 read yb 0 10 bl trp act xa xa 00 qb0 qb1 qb2 qb3 a0-9,11-12 a10 ba0-1 dq auto-precharge interrupted activate [full page burst] full page burst length is available for only the sequential burst type. full page burst read or write is repeated untill a precharge or a burst terminate command is issued. in case of the full page burst, a read or write with auto-precharge command is illegal. [single write] when single write mode is set, burst length for write is always one, independently of burst length defined by (a2-0).
integrated silicon solution, inc. ? 1-800-379-4774 25 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) auto refresh single cycle of auto-refresh is initiated with a refa (/cs= /ras= /cas= l, /we= /cke= h) command. the refresh address is generated internally. 8192 refa cycles within 64ms refresh 256m bit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh, all banks must be in the idle state. auto-refresh to auto- refresh interval is minimum trfc. any command must not be supplied to the device before trfc from the refa command. au to -ref r esh clk? /cs? /ras? /cas? /we? nop or deselect minimum trfc cke a 0-12 b a0-1 auto refresh on all banks auto refresh on all banks
26 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input . all other inputs including clk are disabled and ignored, so that power consumption due to synchro- nous inputs is saved. to exit the self-refresh, supply- ing stable clk inputs, asserting desel or nop com- mand and then asserting cke=h. after trfc from the 1st clk egde following cke=h, all banks are in the idle state and a new command can be issued, but desel or nop commands must be asserted till then. se l f-r e fr e s h clk /cs /ras /cas /we cke a0-12 b a0-1 x 00 new command stable clk nop self refresh entry self refresh exit minimum trfc for recovery
integrated silicon solution, inc. ? 1-800-379-4774 27 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. ext.clk cke int.clk tih tis tih tis po w e r d o w n b y c k e clk cke c ommand cke c ommand d q su sp en d b y ck e clk standby power down active power down pre nop nop nop nop nop nop act write read d0 d1 d2 d3 q0 q1 q2 q3 cke command dq

28 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) dqm control dqm is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqm(u,l) masks input data word by word. dqm(u,l) to write mask latency is 0. during reads, dqm(u,l) forces output to hi-z word by word. dqm(u,l) to output hi-z latency is 2. d qm f unc tio n write read d0 d2 d3 q0 q1 q3 clk command dqmu/l dq masked by dqmu/l=h disabled by dqmu/l=h
integrated silicon solution, inc. ? 1-800-379-4774 29 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) absolute maximum ra tings
symbol vdd parameter supply voltage conditions w ith respect to vss ratings -0.5 - 4.6 unit v vddq supply voltage for output w ith respect to vssq -0.5 - 4.6 v vi input voltage w ith respect to vss -0.5 - 4.6 v vo output voltage w ith respect to vssq -0.5 - 4.6 v io output current 50 ma pd power dissipation ta = 25? c 1000 mw topr operating temperature 0 - 70 ?c tstg storage temperature -65 - 150 ?c recommended opera ting conditions (ta=0 - 70 ?c ,unless otherwise noted) symbol parameter limits unit min. typ. max. vdd supply voltage 3.0 3.3 3.6 v vss supply voltage 0 0 v vddq supply voltage for output 3 . 0 3.3 3.6 v vssq supply voltage for output 0 0 0 v vih*1 high-level input voltage all inputs 2.0 vddq +0.3 v vil*2 low-level input voltage all inputs -0.3 0.8 v cap acit ance (ta=0 -70 ?c,vdd=vddq=3.30.3v,vss=vssq=0v,unless otherwise noted) symbol parameter test condition limits (min.) limits (max.) unit -6 /-7 -75 ci(a) input capacitance, address pin @ 1mhz 1.4v bias 200mv swing vcc=3.3v 2.5 3.8 5.0 pf ci(c) input capacitance, contorl pin 2.5 3.8 5.0 pf ci(k) input capacitance, clk pin 2.5 3.5 4.0 pf c i / o input capacitance, i/o pin 4.0 6.5 6.5 pf 0
30 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) a verage suppl y current fr om vdd (ta=0 - 70?c, vdd=vddq=3.30.3v,vss=vssq=0v, unless otherwise noted) note:
1.address are changed 3 times during trc , only 1 bank is active & all other banks are idle
2.all banks are idle
3.input signals are changed one time during 3x tclk
4.input signals are stable
5.all banks are active
ac opera ting conditions and characteristics
(ta=0 - 70?c, vdd=vddq=3.30.3v,vss=vssq=0v, unless otherwise noted) symbol parameter test conditions l imits unit min. max. voh (dc) high-level output voltage (dc) ioh=-2ma 2.4 v vol (dc) low-level output voltage (dc) iol= 2ma 0.4 v ioz off-state output current q floating vo=0 - - v d d q -10 10 a i i input current vih = 0 -- vddq +0.3v -10 10 a - - item symbol organi- zation limits (max.) unit note -6 -7 -75 operating current icc1 trc=min, tclk=min bl=1,iol=0ma 1 x8 110 ma x16 130 130 ma precharge standby current in non-power down mode icc2n cke=vilmax tclk=15ns x8/x16 20 20 20 ma 2,3 icc2ns cke=vihmin clk=vilmax(fixed) x8/x16 15 15 15 ma 2,4 precharge standby current in power down mode icc2p cke=vihmin tclk=15ns(note) x8/x16 2 2 2 ma 2 icc2ps cke=vihmin tclk=vilmax(fixed) x8/x16 2 2 2 ma active standby current icc3n cke=/cs=vihmin tclk=15ns(note) x8/x16 30 30 30 ma 3,5 icc3ns cke=vihmin tclk=vilmax(fixed) x8/x16 20 20 20 ma 4,5 burst current icc4 all bank active tclk = min bl=4, cl=3, iol=0ma 5 x8 - 150 ma x16 160 160 ma auto-refresh current icc5 trc=min, tclk=min x8/x16 160 160 160 ma self-refresh current icc6 cke < 0.2v x8/x16 -6,-7,-75 3 3 3 ma - - - - -
integrated silicon solution, inc. ? 1-800-379-4774 31 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) ac timing requirements? (ta=0 - 70?c, vdd=vddq=3.30.3v,vss=vssq=0v, unless otherwise noted) input pulse levels:0.8v-2.0v
input timing measurement level:1.4v
clk 1.4v dq 1.4v any ac timing is referenced to the input signal passing through 1.4v. symbol parameter limits unit -75 tclk clk cycle time cl=2 cl=3 tch clk high pulse width ns tcl clk low pulse width tt transition time of clk tis input setup time (all inputs) tih input hold time (all inputs) trc row cycle time trcd ro w to column delay tras row a ctive time trp row precharge time twr write recovery time trrd act to act delay time trsc mode register set cycle time tref refresh interval time max. 10 7.8 120k trfc refresh cycle time min. 10 7.5 2.5 1.8 1 2.5 1 67.5 45 20 15 15 15 20 75 ns ns ns ns ns us ns ns ns ns ns ns ns ns ns max. 10 7.8 120k min. 7 2.5 2.5 1.8 1 1 63 45 20 14 14 14 20 70 - -7 -6 10 max. 7.8 120k min. 2 1.8 1 1 60 6 2 - 15 42 15 12 12 12 60
32 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) switching characteristics? (ta=0 - 70?c, vdd=vddq=3.30.3v,vss=vssq=0v, unless otherwise noted) note: 1. if clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter. output load condition clk 1.4v v out 50pf dq 1.4v output timing measurement reference point clk 1.4v tolz dq 1.4v tac toh tohz s ymbol parameter limits unit note -6 -7 -75 min. max. min. max. min. max. tac access time from clk cl=2 6 ns *1 cl=3 5 5.4 5.4 ns toh output hold time from clk cl=2 3 ns cl=3 2.5 2.7 3 ns tolz delay time , output low- impedance from clk 0 0 0 ns tohz delay time , output high- impedance from clk 2.5 5 2.7 5.4 3 5.4 ns
integrated silicon solution, inc. ? 1-800-379-4774 33 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) bu rs t w ri te (si n g l e ban k) [bl = 4] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc trcd tras twr trp trcd twr 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 write#0 pre#0 act#0 write#0 pre#0 italic p a r a m a te r shows minimum case
34 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) bu rs t w ri te (mu l ti ban k) [bl = 4] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc trcd tras twr trp trcd twr x x x 1 trrd trcd y 1 d1 d1 d1 d1 x x x 1 trc 3 2 6 5 8 c lk? / cs? / ras? / cas? / we? c ke? d qm? a 0 -9, 11? a 10? a 12? b a0 , 1? d q act#0 write#0 pre#0 act#0 write#0 pre#0 act#1 writea#1 act#1 (auto-precharge) italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 35 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) bu rs t r ead (si n g l e b an k) [c l = 2 , bl = 4] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 q0 q0 q0 q0 0 x y x x 0 0 q0 q0 q0 q0 0 trc trcd tras trp trcd tras 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 read#0 pre#0 act#0 read#0 pre#0 italic p a r a m a te r shows minimum case
36 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) bu rs t r ead (mu l ti b an k) [c l = 2 , bl = 4] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 q0 q0 q0 q0 1 x y x x 0 0 q0 q0 q0 q0 0 trc trcd trcd x x x 1 trrd y q1 q1 q1 q1 trcd x x x 1 trc tras 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 reada#0 act#0 read#0 pre#0 act#1 reada#1 act#1 italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 37 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) wr it e i nt e r r up te d by w r i te [b l= 4 ] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 1 y 0 d0 d0 d0 d0 0 trcd x x x 1 trrd y d0 d1 d1 d1 x x x 1 y 0 twr 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 write#0 write#0 writea #1 write#0 pre#0 interrupt interrupt interrupt act#1 same bank other bank other bank act#1 italic p a r a m a te r shows minimum case
38 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) re ad i n te r ru p te d b y rea d [cl = 2, bl = 4] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 q0 q0 1 y 0 q1 q1 q0 q0 trcd x x x 1 trrd y q0 q1 q1 q1 x x x 1 y 1 trcd q0 q0 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 read#0 read#1 reada#1 read#0 interrupt interrupt interrupt act#1 other bank same bank other bank act#1 italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 39 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) wr it e i nt e r r up te d by r e a d , r e a d in te r r upt e d by wr it e [c l= 2 , b l= 4 ] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 y 1 d1 d1 d1 d1 1 trcd x x x 1 trrd q1 q1 y 1 twr trcd 3 2 6 5 8 c lk? / cs? / ras? / cas? / we? c ke? d qm? a 0 -9, 11? a 10? a 12? b a0 , 1 d q act#0 write#0 read#1 write#1 pre#1 act#1 italic p a r a m a te r shows minimum case
40 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) wr it e / r e a d te r m in a te d by pr e c ha r ge [c l= 2 , b l= 4 ] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 y 0 q0 q0 0 trcd 0 twr x x x 0 trp 0 tras trcd trp x x x trc 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 write#0 pre#0 act#0 read#0 pre#0 act#0 terminate terminate italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 41 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) w ri te / re ad t e r mi n a ted b y bu rs t t er mi n a te [cl = 2, b l = 4 ] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 y 0 q0 q0 0 trcd y 0 d0 d0 d0 d0 twr 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 write#0 tbst read#0 tbst write#0 pre#0 italic p a r a m a te r shows minimum case
42 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) si n g l e w r i te b u r st rea d [cl = 2, bl = 4] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 q0 q0 trcd q0 q0 y 0 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 write#0 read#0 italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 43 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) pow e r -u p se qu e n c e a nd in tia liz e c lk 0 0 0 0 ma x x x 200 0 0 0 0
44 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) a u to r e fr e s h 0 1 4 7 9 10 11 12 13 14 15 16 y 0 d0 d0 d0 d0 x x x 0 trp trfc trcd 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q pre all refa act#0 write#0 all banks must be idle before refa is issued. italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 45 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) sel f ref r esh 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 trp trfc 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q pre all self refresh entry self refresh exit act#0 all banks must be idle before refs is issued. italic p a r a m a te r shows minimum case
46 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) c lk sus pe ns io n [c l = 2 , b l= 4 ] 0 1 4 7 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 q0 q0 trcd q0 y 0 d0 d0 d0 q0 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q act#0 write#0 internal clk read#0 internal clk suspended suspended italic p a r a m a te r shows minimum case
integrated silicon solution, inc. ? 1-800-379-4774 47 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) po w e r d o w n 0 1 4 7 9 10 11 12 13 14 15 16 x 0 x x standby power down active power down 3 2 6 5 8 c lk
/ cs
/ ras
/ cas
/ we
c ke
d qm
a 0 -9, 11
a 10
a 12
b a0 , 1
d q pre all act#0 italic p a r a m a te r shows minimum case
48 integrated silicon solution, inc. ? 1-800-379-4774 rev. d 11/01/05 issi ? is42s83200a (4-bank x 8,388,608 - word x 8-bit) is42s16160a (4-bank x 4,194,304 - word x 16-bit) ordering information commercial range: 0c to +70c frequency speed (ns) order part no. package 166 mhz 6 is42s16160a-6t 54-pin tsop-ii 143 mhz 7 is42s16160a-7t 54-pin tsop-ii 133 mhz 7.5 IS42S83200A-75T 54-pin tsop-ii commercial range: 0c to +70c, lead-free frequency speed (ns) order part no. package 166 mhz 6 is42s16160a-6tl 54-pin tsop-ii 143 mhz 7 is42s16160a-7tl 54-pin tsop-ii 133 mhz 7.5 IS42S83200A-75Tl 54-pin tsop-ii
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 1 rev. c 01/28/02 plastic tsop 54?pin, 86-pin package code: t (type ii) plastic tsop (t - type ii) millimeters inches symbol min max min max ref. std. no. leads (n) 54 a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 ? ? ? ? b 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.0083 d 22.02 22.42 0.867 0.8827 e1 10.03 10.29 0.395 0.405 e 11.56 11.96 0.455 0.471 e 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 l1 ? ? ? ? zd 0.71 ref

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